Main Paramedrau Technegol
prosesydd
CPU: 32-bit ARM SC000 Timer: 2 pieces 16/32bit Timers System clock: clock source 40MHz External clock: 1MHz~10MHz
cof
Ram: 10K Bytes
EEPROM:
80KBytes
Yn fwy na 500,000 times erase and write Data retention time is greater than 30 flynyddoedd Support page wipe/page write ROM: 320 KBytes (user 280Kbytes, CMS 40Kbytes)
rhyngwyneb
ISO / IEC 14443 TYPEA: Supports frame reception/frame transmission Support bit-wise anti-collision Support hardware processing 14443-3 instructions and logical encryption authentication instructions Highest communication rate 848kbit/s
ISO / IEC 7816: Compatible with ISO/IEC 7816 T=0/T=1 protocol Support for forward and reverse conventions configurable Parity mode configurable
GPIO: 4
Electrical Characteristics Work field strength: 1.5A/m~7.5A/m
foltedd Gweithio: 1.62V~5.5V
tymheredd gweithio: -25℃ ~ + 85 ℃
ADC: >4000V
Card Parameters
maint: CR80 card L 85.6×W 54×T 0.84(± 0.4)mm
deunydd: PVC / ABS / PET / PETG / PHA, 0.13gwifren gopr mm
Proses amgáu: MF2D80
HCJ72B model chip is a dual-interface smart IC card chip developed by China Chip Design Company and compatible with J3A081 and J3H081 JAVA chips. The HCJ72B chip CPU is ARM's 32-bit SC000. It uses EEPROM data storage. Support ISO/IEC 14443 TYPEA, ISO / IEC 7816 T=0/T=1 communication protocol. Supports DES/3DES, SSF33, SM1/SM2/SM3/SM4, and RSA hardware algorithms. Meet the financial payment chip security requirements.
Prif gais Resident health City bus Micropayment Financial standard payment
Fung
Rheolwr Gwerthiant